学び直し14日目：3章 順序回路⑤（3章完了）

記録

手間取ったけど、全部書けた。やっと次の章に行ける！

• PC の実装。API の If 文の優先順位に従って処理が実施されるようにすればよい。つまり、「reset > load > inc > 現状維持」の優先度。「reset Or load Or inc」でレジスタへの書き込みが発生するような回路も書く必要がある(load が複数の箇所で同じ言葉で使われててわかりづらいな…)。
• RAM512, RAM4K, RAM16K の実装。アドレスの扱い方を理解できてれば、構造自体はすべて同じで楽チン。
• 記述したい回路をいくつかのブロックに区切って、それらを別々に記述するとよさげ。まだ結線図を書いて視覚的にイメージしないと HDL 書けないけど、慣れたら HDL だけでイメージ膨らむんだろうな。

PC

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl

/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

CHIP PC {
    IN in[16],load,inc,reset;
    OUT out[16];

    PARTS:
    // Put your code here:
    Register(in=regin, load=regload, out=out, out=fb);

    Mux16(a=w1, b=false, sel=reset, out=regin);
    Mux16(a=w2, b=in, sel=load, out=w1);
    Mux16(a=fb, b=fbinc, sel=inc, out=w2);

    Inc16(in=fb, out=fbinc);

    Or(a=w3, b=reset, out=regload);
    Or(a=inc, b=load, out=w3);
}

RAM

RAM512

// This file is part of the materials accompanying the book 
// "The Elements of Computing Systems" by Nisan and Schocken, 
// MIT Press. Book site: www.idc.ac.il/tecs
// File name: projects/03/b/RAM512.hdl

/**
 * Memory of 512 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
    // Put your code here:
    RAM64(in=in, load=load0, address=address[0..5], out=w0);
    RAM64(in=in, load=load1, address=address[0..5], out=w1);
    RAM64(in=in, load=load2, address=address[0..5], out=w2);
    RAM64(in=in, load=load3, address=address[0..5], out=w3);
    RAM64(in=in, load=load4, address=address[0..5], out=w4);
    RAM64(in=in, load=load5, address=address[0..5], out=w5);
    RAM64(in=in, load=load6, address=address[0..5], out=w6);
    RAM64(in=in, load=load7, address=address[0..5], out=w7);
    Mux8Way16(a=w0, b=w1, c=w2, d=w3, e=w4, f=w5, g=w6, h=w7, sel=address[6..8], out=out);

    DMux8Way(in=load, sel=address[6..8], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
}

RAM4K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    // Put your code here:
    RAM512(in=in, load=load0, address=address[0..8], out=w0);
    RAM512(in=in, load=load1, address=address[0..8], out=w1);
    RAM512(in=in, load=load2, address=address[0..8], out=w2);
    RAM512(in=in, load=load3, address=address[0..8], out=w3);
    RAM512(in=in, load=load4, address=address[0..8], out=w4);
    RAM512(in=in, load=load5, address=address[0..8], out=w5);
    RAM512(in=in, load=load6, address=address[0..8], out=w6);
    RAM512(in=in, load=load7, address=address[0..8], out=w7);
    Mux8Way16(a=w0, b=w1, c=w2, d=w3, e=w4, f=w5, g=w6, h=w7, sel=address[9..11], out=out);

    DMux8Way(in=load, sel=address[9..11], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
}

RAM16K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
    // Put your code here:
    RAM4K(in=in, load=load0, address=address[0..11], out=out0);
    RAM4K(in=in, load=load1, address=address[0..11], out=out1);
    RAM4K(in=in, load=load2, address=address[0..11], out=out2);
    RAM4K(in=in, load=load3, address=address[0..11], out=out3);
    Mux4Way16(a=out0, b=out1, c=out2, d=out3, sel=address[12..13], out=out);

    DMux4Way(in=load, sel=address[12..13], a=load0, b=load1, c=load2, d=load3);
}

今日の筋トレ

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